Senior Analog Layout Engineer

JD for the Role- Senior Analog Layout Engineer
Experience: 3 + Years, Location: Bangalore/Chennai
Analog layout requirement for SERDES IP being done in 7nm and 10nm. Scope involves scratch layout design.
Below is…

Website Santane Limited

JD for the Role- Senior Analog Layout Engineer
Experience: 3 + Years, Location: Bangalore/Chennai
Analog layout requirement for SERDES IP being done in 7nm and 10nm. Scope involves scratch layout design.
Below is the job description:

Tasks & Responsibilities:

  • This position requires 6+ Industry experience and has worked on 7nm/10nm analog/custom layout.
  • Good understanding of analog concepts along with experience in layout design of complex analog circuits is required.
  • Should have worked in Layout of any one of the following is required : Power Management blocks, PLL, PHY, LDO, high performance ADCs, high speed IO’s or Standard cells, integration and taking the block from specification to release.
  • Responsibilities will include floor planning, DRC/LVS verification and fix, Reliability Analysis and fix, implementation.
  • Should have good debugging skills.
  • Hands-on experience with Cadence tools for custom layout.
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